Sai Kaushik S

Hardware Enthusiast

About Me

  • I am pursuing Dual Degree (B. Tech + M. Tech) in Computer Science and Engineering at Indian Institute of Information Technology, Design and Manufacturing, Kancheepuram, Chennai.

  • Passionate about VLSI Design, Computer Architecture and Reconfigurable Computation.

  • Want to utilize my skills to achieve real world targets, pipelined with increasing my knowledge in the topics.



Resume

Curriculum Vita

Education

July 2018 - Present

Dual Degree (B. Tech + M. Tech) Computer Science and Engineering

Indian Institute of Information Technology Design and Manufacturing Kancheepuram, Chennai

CGPA: 8.79 / 10

July 2016 - April 2018

Class 12 (Karnataka State Board)

Vidya Vardhaka Sangha Sardar Patel Pre-University College, Bangalore

Percentage: 93.33%

July 2015 - May 2016

Class 10 (CBSE Board)

Narayana e-Techno School Ramamurthy Nagar, Bangalore

CGPA: 10 / 10

Skills

Proficiency

Skills

  • C
  • C++
  • Python
  • Verilog
  • Lua
  • Kotlin
  • ARM
  • Git
  • Languages
    • English (Full Professional Proficiency)
    • Hindi (Limited Working Proficiency)
    • Telugu (Native / Bilingual Proficiency)
    • Kannada (Native / Bilingual Proficiency)
    • Tamil (Elementary Proficiency)

Projects

My Works

  • Lorenz Attractor Parallization Algorithm


    C program for visualization of Lorenz Attractor using OpenMP, MPI, CUDA C/C++ and OpenGL for High Performance Computing.

    Build Passing
    Language C
    Dependencies Latest


  • VLIW Simulator


    A Python - Verilog combination that simulates the working of a 32-bit 5-stage pipelined VLIW processor from input assembly code while monitoring the updates in the processor register file.

    Build Passing
    Language Verilog
    Dependencies Latest


  • Key Distribution Centre (Kerberos)


    A multi-threaded GUI application for the client – server communication which uses a Kerberos encryption mechanism for a secure connection.


    Build Passing
    Language Python
    Dependencies Latest


  • Netlist Viewer and Simulator


    A python program that generates a graph from a input verilog .v file, (structural model) or verilog netlist .vm file (Output simulation and Application of TMR approach).

    • Verilog (.v)
    • Verilog Netlist (.vm)

    Build Passing
    Language Python
    Dependencies Latest


  • Sim File Generator


    A python program that generates a .sim file from a input boolean expression


    Build Passing
    Language Python
    Dependencies Latest








  • Dadda Multiplier


    Applications that implements the fast Dadda multiplier with different compression ratios


    • 5:2
    • 15:4
    • 4:2
    Build Passing
    Language Verilog
    Dependencies Latest


Contact

Say Hello

Personal Info

Give me a call

Mobile : +91 95917 16202

Let's connect

Email: saikaushik609@gmail.com ssaikaushik0802@gmail.com ced18i044@iiitdm.ac.in